This invention relates to a tunnel field effect transistor (TFET).
TFETs are a known alternative to bulk MOSFETs, and can offer a number of advantages. For example, they can be highly scalable, do not suffer from short channel effects, can have low off-state currents, can have extremely steep off- to on-state transitions, and can be immune from the effects of random lithographic variations on feature dimensions.
A known kind of TFET is illustrated in FIG. 1. The TFET is incorporated into a semiconductor substrate 2 and includes a source 4, a drain 6 and a gate 10. The source, drain and gate are each provided with contacts 14, 16 and 12. A body contact 18 can also be provided on a rear surface of the substrate 2. A layer of gate oxide 20 is provided on a major surface 8 of the substrate, to electrically isolate the gate 10 from the substrate. The region of the substrate immediately beneath the gate forms a channel region of the device. The source 4 and drain 6 are of opposite conductivity types. In particular, for a p-type substrate, the source 4 can be p+ doped, while the drain 6 can be n+ doped. Typically, the source comprises a material having a smaller band gap than Si, such as Ge or SiGe, which allows the device to deliver reasonable on-state current. The TFET shown in FIG. 1 is an n-type TFET, however p-type TFETs are also known.
The tunnelling operation of the TFET of FIG. 1 is schematically illustrated in FIG. 2. As shown, the tunnelling mechanism occurs at the interface between the gate oxide 20 and the channel, where an inversion layer 3 induced in the channel region by the gate potential touches the source 4. Accordingly, it will be understood that the tunnelling mechanism occurs in a single, point-like region of the device. The limited area at which tunnelling can occur limits the on-state current of the device. Moreover, it will be understood that the performance of the device is heavily reliant upon the characteristics of this point. In particular, imperfections in the device which coincide with this point-like region can lead to degradation in device performance, leading to reliability issues.
As shown in FIGS. 1 and 2, gate oxide 20 covers the channel region, the source 4 and the drain 6. A problem with this design is that while high quality oxide can be formed from the surface of the part of the substrate forming the channel region (which typically may comprise Si), it is difficult to produce high quality oxide from the SiGe or Ge of the source.
Moreover, it is difficult to produce the thick portion (e.g. 300-400 nm) of SiGe or Ge required for the source 4 of the device of FIGS. 1 and 2, even using advanced epitaxial techniques. Preferably, the transition between the source and the substrate should be sharp and well defined. However, the difficulty in producing the thick source region can preclude such a sharp transition.
The above mentioned difficulties, relating to the oxide layer on the substrate surface and to the provision of a thick SiGe or Ge source 4, both increase the likelihood that defects and imperfections will coincide with the single, point-like tunnel region of the device, leading to performance degradation and a large variation on device characteristics.
It is thought that these problems are behind the poor performance of TFET devices compared to theoretical predictions.